![]() Therefore the output pulse width is given by:įigure 3 shows the range of pulse widths available for the various members of the DS1020/DS1021 The propagation delay of the output gate (see diagram next page). The falling edge will be dependent on the programmed delay of the DS1020/DS1021 and The rising edge of the output will be delayed with respect to the input by the propagation delay through Low states of the input must be greater than the delay time of the DS1020/DS1021 which corresponds to In the example shown above the output pulse is triggered by the rising edge of the input waveformĪnd can be adjusted in duration from 10ns (the latent delay of the DS1020/DS1021) up to the maximumįor correct operation over the full range of desired output pulse widths, the duration of both the high and The DS1020/DS1021 can be combined with some simple external logic to produce a programmable pulse Unless reference is made to specific inputs, the same configuration can be used in either the serial or NOTE: In some of the following applications control and/or data input pins have been omitted for clarity. An Enable pin isĪvailable to latch in the serial data once it has been loaded, or to load parallel data and isolate the deviceįrom further changes to a shared parallel bus. A Mode Select pin (S) determines which mode of operation is to be used. ![]() The delay time can be programmed either by means of a serial data input or can be loaded into an 8-bit Of the input waveform are delayed by the same amount. Reappear at the output after a delay time set by the device programming. This is the "normal" mode of operation for the DS1020/DS1021. Product Selection (all times in ns) Part Number
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